1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor memory device which in particular has a MONOS structure of a two bits per cell system, and such semiconductor memory device.
2. Background Information
As an example of a conventional semiconductor memory device, there is a so called stack type nonvolatile semiconductor memory device which includes a floating gate electrode and a control gate electrode, and stores data by accumulating electric charges into the floating gate (e.g. Japanese Laid-Open Patent Application No. 10-223783 (hereinafter to be referred to as Patent Reference 1)).
In such stack type nonvolatile semiconductor memory device, data is written into the floating gate electrode by letting a Fowler-Nordheim current flow into the floating gate electrode from a semiconductor substrate by impressing voltages to the semiconductor substrate, a source and a drain formed on the semiconductor substrate, and the control gate electrode, respectively.
On the other hand, there is another type of conventional nonvolatile semiconductor memory device which has been developed with the intention of miniaturizing the device, and has a so called MONOS (metal oxide nitride oxide silicon) structure where a nitride film is used as a charge storage portion instead of the floating gate electrode.
The conventional nonvolatile semiconductor memory device having the MONOS structure includes a structure in which a dielectric body of a multilayer structure is formed between a semiconductor layer (e.g. a silicon substrate) where a channel is formed and the floating gate electrode (e.g. Japanese Laid-Open Patent Application No. 2003-78045 (hereinafter to be referred to as Patent Reference 2)). This multilayer structure, for instance, has a silicon nitride film and two silicon oxide films (i.e. first and second silicon oxide films) sandwiching the silicon nitride film.
Here, the silicon nitride film in the dielectric body functions as a charge storage portion. The first silicon oxide film formed between the semiconductor layer and the silicon nitride film functions as a potential barrier between the semiconductor layer and the silicon nitride film. On the other hand, the second silicon oxide film formed between the silicon nitride film and the floating gate electrode functions as a film for preventing the electric charges stored in the silicon nitride film from leaking toward a side of the floating gate electrode, unnecessary electric charges from flowing into the silicon nitride film from the floating gate electrode, and so forth.
Writing data to the silicon nitride film described above can be conducted by impressing writing potentials to the floating gate electrode and to a drain region, which is formed in the semiconductor layer as being adjacent to the floating gate electrode under the floating gate electrode, respectively. At this time, a reference voltage or such can be impressed to a source region. By impressing voltages in this way, a channel is formed in the semiconductor layer underneath the floating gate electrode, and carriers bursting out of the drain region flow into this channel. These carriers turn into hot carriers by being accelerated on the side of the source region. The hot carriers generated here penetrate through the first silicon oxide film functioning as a potential barrier. Then the hot carriers, having penetrated through the first silicon oxide film, are trapped and stored in the silicon nitride film functioning as a charge storage portion. In this way, data writing to the silicon nitride film is conducted.
By applying such MONOS structure described above, it is possible to manufacture a so called two bits per cell system nonvolatile semiconductor memory device which stores two bits in a single cell.
In this two bits per cell system nonvolatile semiconductor memory device, a dielectric body having a multilayer structure in which a silicon nitride film is sandwiched between two silicon oxide films (i.e. first and second silicon oxide films), is formed on a semiconductor layer along each side of a floating gate electrode.
However, according to the conventional method of writing with respect to the nonvolatile semiconductor memory device having a MONOS structure, the dielectric bodies on both sides of the floating gate electrode will not have electric fields in a vertical direction impressed thereto due to structural factors. Therefore, particularly as for the electric field in the vertical direction impressed to the dielectric body formed on the semiconductor layer, i.e., the electric field that leaps across the first silicon oxide film that functions as a potential barrier, there are merely vertical components in an electric field leaking from the floating gate electrode.
If there are merely vertical components in the electric field leaking from the floating gate electrode as the electric field is impressed to the dielectric body, even when hot carriers are implanted having energy surpassing the potential of the potential barrier where an interface between the semiconductor layer and the first silicon oxide film is formed, there is a possibility that these hot carriers will not be able to reach the silicon nitride film or an interface between the first silicon oxide film and the silicon nitride film, and will be trapped in the first silicon oxide film. In this case, if the semiconductor layer is a silicon substrate, for instance, a potential barrier of approximately 3.2 eV (electron volt) will be formed in the interface between the silicon and the silicon oxide.
The hot carriers trapped in the first silicon oxide film in the above described way can possibly escape through the first silicon oxide film easily by leaving them at high temperature. In other words, there is a possibility that the conventional structure does not have a sufficient charge retention characteristic to cope with high temperature abandonment.
Both Patent References 1 and 2 show a structure which does not have sidewalls on the sides of the floating gate electrode for the purpose of charge storage, and therefore, these cases are not subjected to the problems mentioned above.
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved method of manufacturing a semiconductor memory device and an improved semiconductor memory device. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.